PCB DFM Checklist: What to Verify Before Fabrication

Design for manufacturability (DFM) is the practice of checking that a board can be fabricated and assembled reliably, at reasonable yield, using the real capabilities of the shops that will build it. A design can pass every electrical rule check in your CAD tool and still be difficult or impossible to build.

A respin is expensive because the cost is more than a second set of boards. You pay again for tooling and setup, lose weeks of schedule, and may scrap assembled parts or stencils tied to the old revision. Most of these problems are cheap to catch in review and expensive to catch on the production floor.

Treat DFM as a gate before release, run against your fabricator's published capabilities rather than generic rules of thumb. Capabilities differ by process, material and shop, so any number in this article is a starting point to confirm, not a guarantee.

Every fabricator publishes minimum trace width and spacing for each copper weight and technology tier. Heavier copper generally needs wider spacing because etching removes more material, so a rule that works on thin copper may not hold on a power layer. Set your design rules from the capability table for the exact copper weight on each layer, then add margin wherever space allows.

Tighter geometry usually moves a board into a more expensive process tier and lowers yield. Where density allows, use relaxed values on non-critical nets and reserve fine geometry for the areas that need it, such as under a fine-pitch BGA.

The annular ring is the copper left around a drilled hole after drilling. Drills wander slightly and layers shift during lamination, so fabricators specify a minimum ring and expect the pad size, finished hole size and tolerance to leave room for that misregistration. Check that every pad stack, especially on vias and mounting holes, meets the fabricator's minimum for its drill size.

Via aspect ratio is the board thickness divided by the finished drill diameter. A deep, narrow hole is harder to plate evenly, so each fabricator states a maximum ratio, often cited in the region of 8:1 to 10:1 for standard processes. A thick board with tiny vias can therefore force a costlier process or a redesign with larger vias or blind and buried structures.

Also confirm that the drill file distinguishes plated from non-plated holes, and that finished hole sizes rather than tool sizes are stated consistently. Mixing the two is a common cause of connectors that do not fit.

Via-in-pad places a via inside a component pad, which helps with fine-pitch BGAs and short power connections. An open via in a pad can wick solder away from the joint during reflow, so these vias are normally filled and capped, which adds cost and process steps. Decide this early and call it out explicitly in the fabrication notes rather than leaving it to inference.

Elsewhere, decide whether vias are tented (covered with solder mask), plugged or left open. Tenting reduces the risk of solder bridges, but whether a tent holds reliably depends on via size and the fabricator's process, so follow their guidance. Vias that must be probed should be explicitly left open.

Solder mask needs a minimum web, the strip of mask between adjacent pads. Where pads sit too close for the fabricator's mask registration, the web is dropped and the openings merge, which raises bridging risk on fine-pitch parts. Check these dams against capability, and keep silkscreen off exposed pads and holes, since ink on a pad can ruin solderability.

Uneven copper distribution can warp boards during lamination and reflow, so aim for reasonably balanced copper about the centre of the stackup, with symmetric layer pairs. Large empty areas on one side with a solid plane on the other are the typical cause. Copper pours in empty areas can help, subject to your signal-integrity needs.

Pads connected directly to large planes act as heat sinks, which makes soldering difficult and encourages cold joints or tombstoned parts. Use thermal relief spokes on plane connections for through-hole and SMD pads, and check spoke width against the current they must carry.

Acid traps are acute-angle copper corners where etchant can pool, leading to over-etching and occasional reliability problems. Avoid sharp acute angles in traces and pour edges, and clean up slivers of copper, which can lift during processing. Most CAD tools can flag both.

Provide a single, closed board outline on a dedicated mechanical layer, with routed slots and cutouts clearly distinguished from the outline. Confirm that units, origin and layer match what your fabrication drawing states. Keep components and copper clear of the edge by the distance the fabricator requires, including near V-score or tab-routing locations.

Panelization affects assembly cost and yield as much as the board itself. Decide with the assembler whether to ship single boards or an array, and which separation method fits: V-score for straight edges, tab routing with perforations for odd shapes. Components that overhang the edge, or tall parts close to a V-score line, can cause problems at depaneling.

Add tooling holes and fiducials as the assembler specifies. Global fiducials on the panel and local ones near fine-pitch parts help pick-and-place alignment; keep the mask opening around each one clear and the copper beneath it consistent.

State the layer count, finished board thickness, copper weight per layer and base material in the fabrication notes. If you do not specify a laminate, the fabricator will choose a default, which may not match what you assumed for impedance, thermal or high-speed needs. Name the material family or the properties you require, such as glass transition temperature for lead-free assembly.

For controlled-impedance nets, agree the stackup with the fabricator before layout is finished, because available prepreg and core thicknesses set what is achievable. List which nets need impedance control, the target values and tolerance, and whether a coupon report is required. The companion article on stackup and impedance control covers this in more depth.

Also specify surface finish, solder mask and silkscreen colour, and the acceptance class you expect, for example a class named in IPC-6012, which your fabricator can confirm they build to.

Design for assembly (DFA) catches problems that only appear when parts meet solder paste and a pick-and-place machine. The highest-value check is footprint verification: overlay each footprint on the manufacturer's recommended land pattern and compare it with the datasheet drawing, not just the part number. A wrong footprint is one of the most common reasons a board cannot be populated.

Check that polarity and pin-1 markings stay visible after assembly, that reference designators are readable and not hidden under components, and that spacing meets the assembler's rules for placement, rework and inspection. Give tall parts and connectors extra room.

Tombstoning, where a small passive stands on one end during reflow, comes from unbalanced heating or mask differences between its two pads. Keep pad sizes symmetrical, avoid tying one pad to a large plane and the other to a thin trace without relief, and follow the land pattern recommendations. Add test points on key nets, reachable from one side and with clearance for fixture probes, so test and bring-up are practical.

Fabricators and assemblers build only what the files say, so the package is part of the design. Generate every file from the same release of a clean project, and open the output in an independent viewer before sending it.

The table below lists the files most shops expect. Ask your fabricator and assembler which formats they prefer, since some favour ODB++ over Gerber.